Turbo decoder architectures for low-density parity-check codes
نویسندگان
چکیده
Absnmt-Tubo deeding oflowdenrily pllityshrek (LDPC) and geme m b e d lowdensity (GLO) coda and the corresponding deeodor amhitoeh m s are mnridrred. A regular (c,r)-LDF'C code of length n is viewed s the interseetion of c intedrrvrd supersods where each smper.de is the dlred sum of n/r indepodent single pa.rity-cheek w b d l s E*dons e GLD coda dmply utilize mom pwellul subsoder. The turbo d d h g schedule is employed to d d e LDPC and GLD coda using constitnmt mR.input soR-mQut (SJSO) deader5 that eommonicste thmugh c inbrlwera. The pmposod xhedule exhibits a faster Convergence behavior, and hence lower decoding latency, than the " m o n l y employed Wo-phase schedule, and hss P reduced memory requirrment that is a Ihnctim of the nomkr of sopercoda. The ~ a r m a n c e of the turbo decoding xhedule is esploaled thmngb dmolationr over an AWGN channel.
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